The present invention relates to a semiconductor and a method for manufacturing the semiconductor, and more particularly, to a method for forming an alignment mark used to align a superimposing film in multilayer wiring.
The higher integration and miniaturization of recent semiconductor devices have decreased the focal depth of exposure in a lithography process when manufacturing a semiconductor device. This has also decreased the tolerable depth of stepped portions. Thus, a chemical mechanical polishing (CMP) process is employed not only to flatten the surface of a film in a global manner but also to form a buried wiring in an insulation film. A plug, which connects layers in a multilayer wiring, may be given as one example of a buried wiring. The CMP process is also widely applied to form such a plug.
When forming a multilayer wiring, the alignment of a pattern, which has been formed on a substrate, with a master pattern, which is transcribed in the lithography process, must be accurately performed.
FIG. 1 illustrates a method for correcting alignment deviation to perform alignment on a semiconductor substrate with high accuracy.
In the prior art, a deviated alignment amount (factor data) is calculated using a sample semiconductor substrate (pilot wafer) of a previous manufacturing lot. The calculated deviated alignment amount is set as an initial value (step S81). An exposure-development process is performed on the pilot wafer of the manufacturing lot that is to undergo exposure (step S82). Then, an alignment measurement of the present pilot wafer is performed, and the factor of the deviation amount obtained through the alignment measurement is analyzed (step S83). The factor data obtained through the factor analysis is considered the factor data of the remaining wafers in the present lot and used as the initial value of the factor data for the next manufacturing lot (step S84). Subsequently, the exposure-development process is performed on the remaining wafers of the present manufacturing lot (step S85). Japanese Laid-Open Patent Publication No. 11-54404 describes a prior art example of such method for correcting the alignment deviation amount.
To correct the alignment deviation amount through the prior art method, the position of an alignment mark formed on a semiconductor substrate must be accurately recognized. FIGS. 2 and 3 illustrate a prior art process for manufacturing a semiconductor device. In the semiconductor device, for example, a plurality of metal oxide semiconductor field effect transistors (MOSFETs) are formed on a silicon substrate, and the MOSFETs are connected to one another by means of multilayer wiring.
[First Operation] (FIG. 2A)
An insulation film 112 is applied to a silicon substrate 111, on which a device 110 is formed. The insulation film 112 is etched to form a hole 113 and an alignment mark (pit) 114. The hole 113 is used to form a buried wiring, which contacts the device 110.
[Second Operation] (FIG. 2B)
A metal film (buried film) 115, which is buried in the hole 113, is deposited on the surface resulting from the first operation so that the metal film 115 is grown to have a uniform thickness.
[Third Operation] (FIG. 2C)
The surface of the metal film 115 undergoes the CMP process until the insulation film 112 is exposed to form a plug 116. The plug 116 is a buried wiring formed by burying the metal film 115 in the hole 113.
[Fourth Operation] (FIG. 3A)
A wiring material is deposited on the surface of the polished metal film 115 and insulation film 112 to form a wiring layer 118. The wiring material is used to form a wiring connected to the plug 116.
[Fifth Operation] (FIG. 3B)
A lithography process is performed to transcribe a mask pattern 119. The position of the alignment mark 114 is referred to when aligning the mask pattern 119. A resist 120 is patterned to etch the wiring layer 118.
A semiconductor device that includes multilayer wiring is normally manufactured by performing the first to fifth operations. However, depending on the film forming condition of each layer, the pit, or the alignment mark 114, may completely be buried in the metal film 115 (FIG. 2C). In such a case, the surface subsequent to the CMP process is completely flattened. This eliminates the stepped portion that reflects the position of the alignment mark 114. Especially, when the wiring material deposited in the fourth operation is, for example, aluminum (Al), the opacity of aluminum hinders the recognition of the alignment mark. In such a case, even if there is a slight surface level difference reflecting the position of the alignment mark 114 subsequent to the third operation, the accuracy for recognizing the alignment mark 114 is not high.
An another prior art process for performing the CMP process to form a plug when the alignment mark pit is over-etched and the etching depth exceeds the thickness of the interlayer insulation film will now be discussed with reference to FIGS. 4 and 5. In the prior art, when forming a pattern of the insulation film, to completely etch an insulation film, for example, the insulation film is rather excessively etched (over-etched) to absorb differences in the etching speed and guarantee the patterning of the insulation film.
When forming a pattern in an insulation film, referring to FIG. 4A, an interlayer insulation film 124 is superimposed on the surface of an insulation film 122 and a wiring 123. The insulation film 122 is formed on the upper surface of an underlayer 121. The wiring 123 is formed in the insulation film 122. A hole 125 and an alignment mark pit 126, which is used for alignment with the hole 125, are formed in the interlayer insulation film 124. The wiring 123, which is connected to a plug 128, is normally arranged at the bottom of the hole 125, in which the plug 128 is formed. When the interlayer insulation film 124 is over-etched, the alignment mark pit 126 extends through the interlayer insulation film 124 and reaches the insulation film 122. The wiring 123 functions as an etching stopper of the interlayer insulation film 124.
Then, referring to FIG. 4B, a metal film (buried film) 127, which is used to form the plug 128, is deposited on the surface including the hole 125 and the alignment mark pit 126.
Subsequently, referring to FIG. 4C, the CMP process is performed to grind the surface of the metal film 127 until the upper surface of the interlayer insulation film 124 is exposed. This forms the plug 128. The deposition and polishing of the metal film 127 forms a stepped portion 129 in the alignment mark pit 126. The stepped portion reflects the position of the alignment mark pit 126.
Referring to FIG. 5A, an Al alloy film 131, which is an upper wiring layer of the plug 128, is deposited on the surface of the plug 128 and the interlayer insulation film 124, which includes the stepped portion 129 and a lower depression 130. A hard mask 132 is deposited on the surface of the Al alloy film 131. In this state, an upper depression 135 is formed above the lower depression 130. The hard mask 132 is used to reinforce a resist 133 and improve the manufacturing accuracy of the wiring when the Al alloy film 131 undergoes etching.
Then, referring to FIGS. 5B and 5C, lithography is performed to form the upper wiring layer (Al alloy film 131) by referring to the upper depression 135 for alignment. That is, the resist 133 is deposited on the hard mask 132, which covers the plug 128. As a result, only the portion of the Al alloy film 131 covered by the patterned resist 133 remains.
In the prior art method, the lower depression 130 is formed at a deep location relative to the surface of the interlayer insulation film 124. Thus, as shown in FIG. 5A, a large portion of the Al alloy film 131 and the hard mask 132 overhangs from the stepped portion of the lower depression 130. Thus, even if the Al alloy film 131 is over-etched, an etching residue 134 may remain in the lower depression 130, as shown in FIG. 5C.
The etching residue 134 may interfere with normal recognition of the alignment mark in subsequent processes. Further, when the etching residue 134 is dispersed on the surface of a film, the dispersed etching residue 134 may cause abnormal forming of the pattern.